The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a heterojunction field-effect transistor using a SiGeC or SiGe layer, and to a method of producing this semiconductor device.
Recently, high integration of a semiconductor device is under way. It is even intended to miniaturize a MOS transistor in which a gate length is below 0.1 .mu.m. In such ultra-miniaturization, however, the current driving ability is saturated due to the influence of a short channel effect or an increase in resistance component. Thus, there cannot be expected such improvements in performance that have hitherto been made. In particular, to increase the driving ability of a miniaturized MOS transistor, it is important to improve the mobility of carriers in a channel and to lower a source-drain electrode in contact resistance.
In view of the foregoing, there has been proposed, instead of a complementary semiconductor device (CMOS device) formed on a silicon substrate, a heterostructure CMOS device (hereinafter referred to as an HCMOS device) using Si/SiGe (mixed crystal of the IV-family elements). The HCMOS device utilizes, as a channel, the interface of a heterojunction structure of two kinds of semiconductors different in band gap from each other, instead of the Si/SiO.sub.2 interface. By using Si/SiGe capable of providing a carrier mobility higher than that provided by Si, it is expected to achieve a transistor higher in operational speed. By controlling the composition of Si/SiGe, it is possible to form, on a Si substrate, an epitaxial growth layer having the desired amount of strain and the desired value of band gap. Ismail of the IBM company has conducted basic experiments on improvements in characteristics of an HCMOS device of the Si/SiGe type (See K. Ismail, "Si/SiGe High Speed Field-Effect Transistors", IEDM Tech. Dig. 1995, p509 and M. A. Armstrong et al, "Design of Si/SiGe Heterojunction Complementary Metal-Oxide Semiconductor Transistors", IEDM Tech. Dig. 1995, p761).
FIG. 15 is a section view of an example of this HCMOS device. As shown in FIG. 15, there is formed, on a portion of a Si substrate 101, a field-effect transistor comprising source-drain regions 109, a gate insulating layer 107 and a gate electrode 110. Formed in a so-called channel region between the source-drain regions under the gate electrode 110 are a SiGe buffer layer 102, a .delta. doped layer 115, a spacer layer 103, an i-Si layer 104, an i-SiGe layer 105 and an i-Si layer 106. In these layers, the SiGe buffer layer 102 gives tensile strain to the i-Si layer 104 for forming an n-channel layer 112 between the SiGe buffer layer 102 and the i-Si layer 104. In the SiGe buffer layer 102, the Ge composition rate is gradually changed such that the Ge composition rate in that portion of the layer 102 immediately above the Si substrate 101 is equal to 0%, while the Ge composition rate in the top portion of the layer 102 is equal to 30%.
When a negative bias voltage is applied, the n-channel layer 112 is formed on the heterointerface between the i-Si layer 104 and the SiGe buffer layer 102 thereunder. The .delta. doped layer 115 is arranged to supply electrons serving as carriers to the n-channel layer 112 which is formed on the .delta. doped layer 115. The spacer layer 103 is arranged to spatially separate the ions in the .delta. doped layer 115 formed below the spacer layer 103, from the n-channel layer 112 formed on the spacer layer 103, thus preventing the carrier mobility from being lowered due to ion scattering.
On the other hand, when a positive bias voltage is applied, a p-channel layer 111 is formed, at the side of the i-SiGe layer 105, on the heterointerface between the i-SiGe layer 105 and the i-Si layer 106 thereon. The gate insulating layer 107 is formed to insulate the gate electrode 110 from the p-channel layer 111.
As discussed in the foregoing, the heterojunction field-effect transistor is characterized in that a channel is formed on the heterointerface between two kinds of semiconductor layers different in band gap from each other. Accordingly, to form a channel, there are inevitably present at least two kinds of semiconductor layers different in band gap from each other. In addition, to form, in semiconductor layers, a channel in which electrons or positive holes move at a high speed, it is required to form, at the heterointerface, a discontinuous portion of a conduction or valence band. In the Si/SiGe type above-mentioned, the i-SiGe layer 105 has a discontinuous portion in the valence band with respect to the i-Si layer 106, thus forming a channel for positive holes (See the left portion of FIG. 15). However, the conduction band hardly has a discontinuous portion. Accordingly, tensile strain is induced in the i-Si layer 104 such that a discontinuous portion is formed in the conduction band at the heterointerface between i-Si layer 104 and the i-SiGe layer 105 (See the right portion of FIG. 15).
According to a simulation, it is estimated that, as compared with a conventional CMOS device in the same size using a Si/SiO.sub.2 channel, the HCMOS device having the arrangement above-mentioned achieves an operation at double the speed with a half power consumption. More specifically, this is a semiconductor transistor in which a Si semiconductor is combined with a SiGe mixed crystal to form a heterointerface and in which there is formed a channel in which carriers are mobile at a high speed. Thus, attention is placed to this semiconductor transistor as a transistor capable of achieving both a high-speed operation utilizing a heterojunction and large-scale integration of a MOS device.
A heterojunction device utilizing a mixed crystal of the IV-family elements such as SiGe is expected as means for overcoming the functional limit of a CMOS device of prior art. Due to the difficulty in production, however, a heterojunction field-effect transistor using a mixed crystal of the IV-family elements represented by SiGe is behind in research and development as compared with a heterojunction bipolar transistor which is a heterodevice similarly using a mixed crystal such as SiGe. Thus, it cannot be stated that studies have sufficiently be made on the structure capable of providing performance as expected and on the method of producing such structure.
Further, in a heterojunction field-effect transistor having a so-called heterojunction MOS structure having an insulating layer between a gate electrode and a semiconductor layer as above-mentioned, a stable and good insulating layer cannot be formed in the SiGe layer. Accordingly, an oxide layer of SiO.sub.2 is used as a gate insulating layer. It is therefore required that a Si layer is always present immediately below the gate insulating layer. However, Si is characterized in that its band gap is always greater than the band gap of SiGe. This is disadvantageous in the above-mentioned HCMOS device of prior art as set forth below.
Firstly, to form an electron channel on the Si substrate 101, tensile strain is induced in the i-Si layer 104 to form a band discontinuous portion at the Si/SiGe heterointerface. However, the lattice constant undergoes a change to induce dislocation due to lattice relaxation.
FIG. 16 is a section view illustrating the SiGe buffer layer 102 and the i-Si layer 104 thereabove, as picked out from FIG. 15. Since the i-Si layer 104 is smaller in lattice constant than the SiGe buffer layer 102, tensile strain will be accumulated at the stage of crystal growth. When such accumulation becomes great, this results in dislocation in the i-Si layer 104 as shown in FIG. 16. Thus, dislocation or line defect is inevitably induced by strain due to lattice misfit between the i-Si layer 104 and the SiGe buffer layer 102. Setting apart from the initial characteristics of a transistor utilizing such a crystal, it is considered that the reliability and life-time of the transistor are influenced by the deterioration in characteristics due to the growth of dislocation in the crystal.
The SiGe buffer layer 102 made of SiGe greater in lattice constant than Si is laminated on the Si substrate 101 and tensile strain is accumulated in the i-Si layer 104 which is grown on the SiGe buffer layer 102. As the thickness of the SiGe buffer layer 102 is increased, the thickness exceeds the critical thickness in which the lattice constant of the SiGe buffer layer 102 is changed from the lattice constant of Si to the original lattice constant of SiGe. This produces lattice relaxation, causing defects such as dislocation or the like to be induced also in the SiGe buffer layer 102.
There are instances where such defects do not exert a significant influence on the initial characteristics of the transistor. In view of long-term reliability and life-time, however, such defects involve a possibility of a serious trouble being caused. More specifically, the transistor is deteriorated due to the growth of defects by an electric current or the diffusion of metal or impurity through the defects, thus possibly causing the transistor to be lowered in reliability.
Secondly, a heterojunction field-effect device using a mixed crystal of the IV-family elements represented by SiGe is effective as a transistor structure capable of overcoming the performance limit of a miniaturized CMOS device of prior art. At this point of time, however, studies on optimization of the contact of each source-drain electrode have not sufficiently been done as compared with studies on improvements in channel mobility. Thus, the structure cannot take full advantage of such high-speed mobility. In the IBM's heterojunction CMOS device technology mentioned earlier, too, detailed studies have been made on improvements in mobility of a channel region, but studies have hardly been made on reduction in resistance of the contact of each source-drain electrode which is another important factor for improvement in performance of a miniaturized transistor.
More specifically, in a CMOS device structure using a single crystal of Si, a variety of studies have been made on the structure of the contact region of the substrate connected to a source-drain electrode. However, studies are required as to whether or not the contact region structure and its production method which are optimized for a general CMOS device, are also good for a heterojunction field-effect device different in transistor structure.